Quantum-dot cellular automata (QCA) are an emerging technology and a possible alternative for faster speed, smaller size, and low power consumption than semiconductor transistor based technologies. Previously, adder designs based on conventional designs were examined for implementation with QCA technology. This paper utilizes the QCA characteristics to design a fault-tolerant adder that is more powerful in terms of implementing robust digital functions. By considering two-dimensional arrays of QCA cells, fault properties of such block adder can be analyzed in terms of misalignment, missing and dislocation cells. In order to verify the functionality of the proposed device, some physical proofs are provided. The results confirm our claims and its usefulness in designing digital circuits.

One of the major problems in designing highly compact integrated circuits is the power consumption of the circuits. Therefore, several technologies have been introduced to overcome the problems facing MOSFET technology. One of these technologies is the Quantum-Dot Cellular Atomata (QCA), which has several advantages. In this paper, we focus on computational logic gates based on the T-Latch circuit. T-latch is the basis of many circuit in arithmetic logic unit (ALU). The proposed structure for T-latch has a lower number of cells, occupied area and lower power consumption than existing methods. In the proposed T-Latch, compared to previous best designs, 6.45% cross section area and 44.49% power consumption were reduced. Also in this paper, for the first time a T-latch with reset terminal and a T-Latch with both set and reset terminals were designed. In addition, using the proposed T-latch, a 3-bit bidirectional up-down counter which consists of 204 quantum cells, 0.26 µm2 cross-sectional area, delay of 5.25 clock cycles, a three-bit up-down counter with a reset pin and a three-bit up-down counter with set and reset terminals were made. The proposed up-down circuits are designed for the first time in QCA technology. All the design and simulation results are done in QCADesigner software.

Complementary metal-oxide semiconductor (CMOS) technology has been the industry standard to implement Very Large Scale Integrated (VLSI) devices for the last two decades. Due to the consequences of miniaturization of such devices (i.e. increasing switching speeds, increasing complexity and decreasing power consumption), it is essential to replace them with a new technology. Quantum-dot cellular automata (QCA) is one of the alternative technologies proposed as a replacement solution to the fundamental limits of CMOS technology. QCA has the potential to be one of the features promising nanotechnologies because of its higher speed, smaller size and lower power consumption in comparison with transistor-based technology. This work proposes optimized QCA RS (Reset Set) flip flops. The proposed structures are simulated and validated using QCA Designer software. In comparison with the previous works the proposed QCA RS flip flops require the minimum number of cells, area and delay. Also, in comparison with CMOS technology our QCA designs are more efficient in terms of area, delay and frequency. Therefore, these structures can be used to design nanoscale circuits.

Quantum-dot cellular automata (QCA) is one of the new technologies in the design of digital nano circuits. This technology is an appropriate alternative to today's silicon technology. The inherent features of this technology include very small dimensions, high speed and very low power consumption. Therefore, it can be used to design special memories that require high operating speed such as the content addressable memory. These types of memory are widely used in designing hardware systems, especially routers. In this type of memory, speedy operations are very necessary due to the large number of search and comparison errands. In this paper, we propose a structure for the content addressable memory in QCA that has a mask capability for comparison. The proposed structure consists of a memory cell, a comparator and a matching unit designed using Multiplexer and XNOR gate. The performance of the designed structure is studied by QCADesigner software. The result proves its effectiveness. The proposed structure has 11% improvement in cell number, 57% improvement in gate number and 5% improvement in area occupancy compared to the previous structure.